Job Description
Position Responsibilities
" Write SystemVerilog/UVM testbenches to verify ASICs and FPGAs.
" Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
" Build functional coverage models and close code coverage gaps.
" Create tests that verify DSP and third-party IP integration.
" Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
" Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
" Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
" Collaborate with system and hardware teams to capture requirements and debug issues.
Required Skills
" Bachelor's degree in EE, CE, CS, or related field (or equivalent experience).
" Experience with ASIC/FPGA verification using SystemVerilog and...
" Write SystemVerilog/UVM testbenches to verify ASICs and FPGAs.
" Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
" Build functional coverage models and close code coverage gaps.
" Create tests that verify DSP and third-party IP integration.
" Run simulations, linting, CDC checks, static timing checks, and gate-level regressions.
" Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
" Support FPGA bring-up, hardware emulation/prototyping, and hardware integration tests.
" Collaborate with system and hardware teams to capture requirements and debug issues.
Required Skills
" Bachelor's degree in EE, CE, CS, or related field (or equivalent experience).
" Experience with ASIC/FPGA verification using SystemVerilog and...