Job Description
Job Description Understand ASIC unit microarchitecture by studying specifications and collaborating with the logical design team. Create and execute verification test plans. Develop verification environments and coverage models using UVM-SystemVerilog/C++. Write and maintain verification specifications. Monitor, analyze, and debug simulation errors. Analyze simulation coverage results and improve tests to achieve coverage targets. Develop reusable and maintainable code across projects. Strong knowledge of Object-Oriented Programming, UVM methodology, SystemVerilog/SystemC, and Constraint-Random/Coverage-Driven verification. Experience with drivers, monitors, checkers, self-checking models, covergroups, and SVA. Familiarity with simulation and coverage visualization tools. Strong problem-solving and root-cause analysis skills.
ASIC Verification Engineer