Job Description
**Position:**
Design Verification Engineer (Einfochips)
**Job Description:**
**Experience: 6+ Years**
**Location: Austin TX and San Jose CA**
**Job Description:**
**What candidate will Be Doing:**
+ At-least **6+ years of experience** in **System Verilog HVL and C++/C**
+ At-least 6+ year of experience in **UVM.**
+ Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
+ Proficient in **SVTB/UVM, C++ testbench**
+ Understand DSP is a plus
+ Subversion for Repository and Bugzilla is also a Plus
+ **Proficient in debug** and assertions coding
+ Verification closure with team
**What We Are Looking For:**
+ At-least 6 **+ years of experience** in **System Verilog HVL and C++/C**
...
Design Verification Engineer (Einfochips)
**Job Description:**
**Experience: 6+ Years**
**Location: Austin TX and San Jose CA**
**Job Description:**
**What candidate will Be Doing:**
+ At-least **6+ years of experience** in **System Verilog HVL and C++/C**
+ At-least 6+ year of experience in **UVM.**
+ Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
+ Proficient in **SVTB/UVM, C++ testbench**
+ Understand DSP is a plus
+ Subversion for Repository and Bugzilla is also a Plus
+ **Proficient in debug** and assertions coding
+ Verification closure with team
**What We Are Looking For:**
+ At-least 6 **+ years of experience** in **System Verilog HVL and C++/C**
...