💼 Full-Time Position

Design Verification Engineer

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ACL Digital
📍 Mumbai, Maharashtra, India
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Location
Mumbai, India
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Posted
June 04, 2026
Type
Full-Time
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Full-Time Opportunity: This is a permanent, full-time position with a competitive package and real career growth potential.

Job Description

Experience: 4-5 Years
Location: Bangalore/Hyderabad
Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics

Roles and Responsibilities

Verilog, System verilog, UVM
VHDL, UVVM
Simulator exposure with VCS, Questa, Xcelium
Proficient in simulation and HW languages
Should be able to interpret various LRMs and comply with semantics and testcase creation.

Share the profiles to [email protected].