Job Description
Join Ciena in Ottawa as a Senior Digital ASIC Design Engineer, focusing on cutting-edge WaveLogic products. This role emphasizes collaboration and high-quality silicon delivery.
The ideal candidate will have more than five years of experience and will be responsible for top-level ASIC design, interpreting functional specifications, and enhancing technology libraries. Collaborating with systems engineers, you'll be crucial in creating innovative telecommunications infrastructure through ASIC integration.
Key Responsibilities:
• Lead ASIC design and integration efforts for advanced technology
• Collaborate with architects to interpret specifications
• Maintain and enhance libraries for semiconductor nodes
• Create and analyze timing constraints for designs
• Perform lab validation tasks for ASIC prototypes
Requirements:
• Bachelor’s in Electrical or Computer Engineering
• Minimum 5 years in ASIC design
• Experience with Verilog, SystemVerilog, and Python<...
The ideal candidate will have more than five years of experience and will be responsible for top-level ASIC design, interpreting functional specifications, and enhancing technology libraries. Collaborating with systems engineers, you'll be crucial in creating innovative telecommunications infrastructure through ASIC integration.
Key Responsibilities:
• Lead ASIC design and integration efforts for advanced technology
• Collaborate with architects to interpret specifications
• Maintain and enhance libraries for semiconductor nodes
• Create and analyze timing constraints for designs
• Perform lab validation tasks for ASIC prototypes
Requirements:
• Bachelor’s in Electrical or Computer Engineering
• Minimum 5 years in ASIC design
• Experience with Verilog, SystemVerilog, and Python<...