Job Description
FPGA Design Verification (DVT) across block, subsystem, and system levels Strong
SystemVerilog + UVM
(testbench architecture, stimulus, coverage) RTL understanding (Verilog/SystemVerilog) with ability to validate against specs Develop
verification plans, test strategies, and coverage models
from architecture Execute
functional, integration, regression, and negative testing Debug complex issues using
waveform analysis, root-cause, expected vs actual Experience with
high-speed interfaces
(PCIe, Ethernet, DDR, SPI, I2C, USB) Exposure to
telecom/wireless (4G, LTE, 5G, O-RAN, 3GPP)
environments Knowledge of
asynchronous clock domains & timing considerations Hands-on with
simulation, regression frameworks, and coverage analysis tools Scripting for automation ( Python, Tcl, Bash ) and CI/CD integration Experience with
Xilinx Vivado or Intel Quartus (Agilex)
toolchains ...
SystemVerilog + UVM
(testbench architecture, stimulus, coverage) RTL understanding (Verilog/SystemVerilog) with ability to validate against specs Develop
verification plans, test strategies, and coverage models
from architecture Execute
functional, integration, regression, and negative testing Debug complex issues using
waveform analysis, root-cause, expected vs actual Experience with
high-speed interfaces
(PCIe, Ethernet, DDR, SPI, I2C, USB) Exposure to
telecom/wireless (4G, LTE, 5G, O-RAN, 3GPP)
environments Knowledge of
asynchronous clock domains & timing considerations Hands-on with
simulation, regression frameworks, and coverage analysis tools Scripting for automation ( Python, Tcl, Bash ) and CI/CD integration Experience with
Xilinx Vivado or Intel Quartus (Agilex)
toolchains ...