IP Design Verification Engineer – UVM/Verilog Expert

A global technology company is seeking a Design Verification Engineer in Penang, Malaysia. This role involves developing verification test plans and metrics for complex designs, requiring strong analytical skills, previous experience with UVM/OVM, and programming skills in languages such as C/C++. Candidates should have at least a BS/MS/PhD in Electronics or Computer Engineering and a minimum of 5 years experience in SystemVerilog or similar verification methodologies. This is an opportunity to join a dynamic team committed to innovation.
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