💼 Full-Time Position

Lead engineer-Design verification

🏢
Uni Connect
📍 singapore, singapore, Singapore
📍
Location
singapore, Singapore
📅
Posted
May 29, 2026
Type
Full-Time
🎯

Full-Time Opportunity: This is a permanent, full-time position with a competitive package and real career growth potential.

Job Description

singapore, Singapore | Posted on 12/02/2024

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

Specific responsibilities include:

  • The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
  • Develop test plans at block, sub-system, and chip level.
  • Execute SoC-based verification at full-chip.
  • Write C-based lib packages and tests.
  • Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
  • Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
  • Automating the test environment for randomized testing and scoreboarding.
  • Utilize advanced debugging techniques to identify and resolve design and verifi...