Job Description
This role is for a Memory Layout Engineer with 3-7 years of experience to design and develop memory blocks for integrated circuits (ICs). You will be responsible for creating efficient memory layouts that meet performance, power, and area constraints.
Responsibilities:
- Design memory layouts for various building blocks including:
- Bit cell array
- Row decoder
- Column decoder
- Sense amplifiers
- Input/Output (I/O) blocks
- Integrate top-level memory blocks
- Perform physical verification using tools like Design Rule Check (DRC) and Layout Versus Schematic (LVS)
- Ensure layouts meet Design for Manufacturability (DFM) and Design for Yield (DFY) requirements
- Analyze layouts for potential power and signal integrity issues
- May involve scripting using languages like PERL, Shell, TCL, or Skill
Qualifications: