Job Description
Elevate your career with Infosys as a Memory Team Layout Lead based in Burnaby, BC. Collaborate with design engineers on memory architectures and layout optimization.
This role requires a Bachelor’s degree or equivalent experience in IT along with 5+ years in Compiler/Custom Memory Layout design. You'll work closely with Registers and Memory Arrays, transforming schematics into optimal layouts. Engage directly with the circuit team to drive innovations in memory layout and enhance performance metrics.
Key Responsibilities:
• Collaborate with circuit team for layout design
• Design Memory Leafcell layout library from scratch
• Optimize layout design for superior performance
• Verify layouts using Cadence Virtuoso and Calibre
• Ensure compliance with DRC, LVS, and ERC standards
Requirements:
• Bachelor's degree or equivalent experience
• Minimum 5 years in Memory Layout design
• Proficiency in Finfet technology
• Familiarity with 3nm and 5nm technologi...
This role requires a Bachelor’s degree or equivalent experience in IT along with 5+ years in Compiler/Custom Memory Layout design. You'll work closely with Registers and Memory Arrays, transforming schematics into optimal layouts. Engage directly with the circuit team to drive innovations in memory layout and enhance performance metrics.
Key Responsibilities:
• Collaborate with circuit team for layout design
• Design Memory Leafcell layout library from scratch
• Optimize layout design for superior performance
• Verify layouts using Cadence Virtuoso and Calibre
• Ensure compliance with DRC, LVS, and ERC standards
Requirements:
• Bachelor's degree or equivalent experience
• Minimum 5 years in Memory Layout design
• Proficiency in Finfet technology
• Familiarity with 3nm and 5nm technologi...