Job Description
RTL Design Verification Engineer
Experience- 3+ years
Location-Bangalore
NP- 0- 15 days
Key Responsibilities
Functional Verification
Develop and execute RTL verification plans based on design specifications and system requirements.
Build, enhance, and maintain System Verilog / UVM‑based testbenches (drivers, monitors, scoreboards, checkers).
Write directed and constrained‑random test cases for functional, corner‑case, and negative testing.
Debug RTL and testbench issues using waveform analysis and simulation tools.
Coverage & Quality Closure
Drive code coverage (line, branch, FSM, toggle) and functional coverage to closure targets.
Analyze coverage gaps and implement additional test scenarios for closure.
Participate in RTL release readiness activities, ensuring verification sign‑off before major RTL drops.