Job Description
About SerdesWorks Pte. Ltd. SerdesWorks is a deep-tech semiconductor startup focused on developing
high-speed SerDes PHY IP and IO die solutions
for next-generation interfaces including DDR5, MIPI, PCIe, and UCIe. We are building advanced PHY solutions in
TSMC 22nm / 12nm and beyond
, targeting high-performance computing, AI accelerators, and chiplet-based systems. Role Overview We are seeking a
Senior Analog Layout Engineer
with strong experience in
advanced process nodes and high-speed SerDes PHY design
to drive full-custom layout implementation of high-performance analog/mixed-signal circuits. This role is critical in ensuring silicon success, signal integrity, and manufacturability of our next-generation IP. Key Responsibilities Perform full-custom layout design for high-speed analog/mixed-signal blocks, including: PLL / CDRTX/RX front-end (driver, CTLE, DFE)Clocking and bias circuits Execute layout in advanced nodes (22nm, e.g. 22nm / 12nm / 6nm) Ensure lay...
high-speed SerDes PHY IP and IO die solutions
for next-generation interfaces including DDR5, MIPI, PCIe, and UCIe. We are building advanced PHY solutions in
TSMC 22nm / 12nm and beyond
, targeting high-performance computing, AI accelerators, and chiplet-based systems. Role Overview We are seeking a
Senior Analog Layout Engineer
with strong experience in
advanced process nodes and high-speed SerDes PHY design
to drive full-custom layout implementation of high-performance analog/mixed-signal circuits. This role is critical in ensuring silicon success, signal integrity, and manufacturability of our next-generation IP. Key Responsibilities Perform full-custom layout design for high-speed analog/mixed-signal blocks, including: PLL / CDRTX/RX front-end (driver, CTLE, DFE)Clocking and bias circuits Execute layout in advanced nodes (22nm, e.g. 22nm / 12nm / 6nm) Ensure lay...