Senior ASIC Timing & Physical Design Engineer

A semiconductor company based in Zürich seeks an experienced ASIC Physical Design Engineer with a strong emphasis on timing closure and sign-off. Responsibilities include maintaining timing constraints, running Static Timing Analysis, and leading ECOs. The role requires 5+ years of relevant experience, familiarity with STA tools, and scripting capabilities. Join a dynamic team and contribute to high-quality designs in a collaborative environment.
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