💼 Full-Time Position

Senior design verification engineer

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Cadence
📍 Noida, Uttar Pradesh, India
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Location
Noida, India
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Posted
June 03, 2026
Type
Full-Time
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Full-Time Opportunity: This is a permanent, full-time position with a competitive package and real career growth potential.

Job Description

Job Title: Principal Software Engineer – VIP (Verification IP)
Location: Noida
Experience: 7-10 yrs
Job Summary
We are looking for a Principal Engineer for our Verification IP (VIP) team to design and develop high-quality VIP solutions for next-generation high-speed protocols. The role involves working on architecture, development, and validation of protocol-compliant VIPs.
Key Responsibilities
- Architect, design, and develop Verification IP (VIP) for industry-standard protocols.
- Lead development of VIP using System Verilog/UVM methodologies
- Define verification strategies, test plans, and coverage models
- Drive protocol compliance, debugging, and performance optimization
- Mentor junior engineers and provide technical leadership
- Work on customer issues, feature enhancements, and next-gen protocol adoption
Required Skills & Experience
- Strong expertise in System Verilog and UVM-based verification
- Proven experience in VIP development /...