Senior Design Verification Engineer — Pre‑Silicon DV Expert

Lattice Semiconductor is looking for a Design Verification Engineer in Penang, Malaysia. This role involves developing test plans, implementing verification environments, and ensuring coverage metrics. Candidates should have a BS/MS/PhD in Electronics or Computer Engineering with at least 5 years of experience in SystemVerilog/UVM. Strong understanding of HDL and programming skills in languages such as C/C++, Perl, or Python are essential. Join a dynamic team and contribute to innovative projects in a supportive environment.
#J-18808-Ljbffr