Senior FPGA IP Design Engineer — High-Speed RTL

Lattice Malaysia is seeking an experienced candidate to lead the development of Connectivity IP portfolios for FPGA. The role requires technical leadership and the ability to create high‑speed RTL designs that maximize performance, power, and logic utilization.

Applicants must have at least 5 years of FPGA IP design experience and possess a degree in Electronics or Computer Engineering. Programming skills in C/C++, Perl, TCL, or Python are highly desirable.