Senior FPGA IP Design Engineer – Lead High-Speed IP

Lattice is seeking a Senior IP Design Engineer in Penang, Malaysia to develop innovative Connectivity IP portfolios for Lattice FPGA. The role involves translating specifications into high-speed RTL design, ensuring optimal performance, power, and logic utilization.

Candidates should possess a BS/MS/PhD in Electronics or Computer Engineering with a minimum of 5 years in FPGA IP design. Programming skills in languages like C/C++, Perl, or Python are required.