Job Description
Principal Accountabilities
* Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis etc in ASIC PNR Flow
*Execute the block level place and route assignments from Netlist through GDS flow
* Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed.
* Close STA timing across all corners and modes for blocks and should be able to generate ECO independently .
* Work with design teams for closing CTS, IO timing, DFT timing.
* Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
*Ensure successful delivery of blocks to customers
Job Complexity
Minimum 5 years experience required in Physical Design
● Requires in-depth knowledge and experience
● Solves complex problems; takes a new persp...