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Full-Time Opportunity: This is a permanent, full-time position with a competitive package and real career growth potential.
Job Description
Job Description:
Job Reference QWY475WW
Job Description
Perform Netlist-to-GDS design flow, including floor planning, placement, timing optimization, clock free synthesis and routingSupport STA timing analysis and fixingPerform physical verification, including DRC, LVS, IR drop and DFM analysisJob Requirement
Graduated in EE/CSFrom 3 years working experiencesToeic 730~855 is preferredFamiliar with Cadence Innovus or Sysnopsys ICC2/Fusion CompilerHave experiences in 65/40/28nm IC design experiences will be plusWhat we offer
Competitive salary packageFree motorbike parkingMonthly meal & transportation allowancesPremium healthcare package applies since probationPremium healthcare package for family member after probationAnnual health check, company trip, voucher/ gifts in...