Job Description
Responsibilities:
- Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
- Worked on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias.
- Provide technical guidance and mentoring to Physical Design Engineers.
- Interface with front-end ASIC teams to resolve issues.
- Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
- Timing closure on DDR2/DDR3/PCIE interfaces.
- Excellent communication skills.
- Strong background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Extensive experience and...