Senior SOC RTL Design Engineer - Low-Power & Verification

A technology company in Singapore is seeking a SOC Design Engineer to join a dynamic SoC Front End Design team. You will design digital logic using VHDL/Verilog and ensure quality RTL meets diverse design requirements. Ideal candidates will have a degree in Electrical/Electronics Engineering and experience in DSM SoC Design processes. This role encourages fresh graduates to apply, supporting a collaborative, diverse environment focused on innovation and high performance.
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