Job Description
We are looking for a skilled Sr. Design Verification Engineer with strong hands-on experience in SV/UVM-based verification.
Key Requirements:
- Strong experience in SystemVerilog/UVM verification methodology
- Ability to derive verification features from specifications and create verification/test plans
- Hands-on experience in building testbench components from scratch
- Good exposure to IP/SoC level verification and coverage closure
- Strong knowledge of AMBA AHB protocol and debugging/root cause analysis
- Experience in writing assertions and handling functional/code coverage
Thanks,
Karthik