Job Description
Join AMD’s SerDes Technology team as a SerDes RTL Design Engineer focused on multi-protocol wireline transceivers. You'll design key digital components while collaborating with cross-disciplinary teams.
Contribute to high-performance design using advanced CMOS processes at AMD. This role emphasizes RTL design for calibration loops, signal processing logic, and clock-data recovery. Work closely with system architects and other engineers to optimize low-power design techniques and achieve PPA excellence.
Key Responsibilities:
• Collaborate on micro-architecture for high-speed SerDes PHY
• Own RTL design for calibration/adaptation loops and DSP logic
• Perform PPA trade-off analysis using low-power techniques
• Develop and validate block-level test benches and functionality
• Run design checks using LINT, CDC, and RDC tools
Requirements:
• Proficient in Verilog/SystemVerilog for RTL coding
• Experience in mixed signal design and low-power design methodology
Contribute to high-performance design using advanced CMOS processes at AMD. This role emphasizes RTL design for calibration loops, signal processing logic, and clock-data recovery. Work closely with system architects and other engineers to optimize low-power design techniques and achieve PPA excellence.
Key Responsibilities:
• Collaborate on micro-architecture for high-speed SerDes PHY
• Own RTL design for calibration/adaptation loops and DSP logic
• Perform PPA trade-off analysis using low-power techniques
• Develop and validate block-level test benches and functionality
• Run design checks using LINT, CDC, and RDC tools
Requirements:
• Proficient in Verilog/SystemVerilog for RTL coding
• Experience in mixed signal design and low-power design methodology