Job Description
Job Responsibilities
- Design digital logic with high-level description language (VHDL/Verilog) from specification
- Design quality RTL that meets all design requirement of input/output requirements, constraints, multiple clock domains, functional modes, and analog blocks
- Design RTL with low power requirement from standard power intent file input
- Design of RTL for SoC and FPGA-friendly and DFT compliant code is critical
- Design of RTL for IP development and SoC assembly
- Design of RTL for SoC Clock & Reset structures is a plus
- Verify the design through extensive test-bench simulation and ability to debug with FPGA prototyping
- Experience with Design For Test requirement is a plus
- Experience with Synthesis, and Logic Equivalent checks are added advantage
- Work with other RTL2netlist and Backend team to resolve any design issues
- Bachelor Degree...