Job Description
Experience - 4 to 11 years
Responsibilities
Design FCI (Fast Cache instances) for x PU (CPU/GPU) systems with the SRAM team.
Define design specs with CPU/GPU/APU teams.
Optimize SRAM for power, timing, area, and yield.
Implement Single Port & Two Port SRAM circuits.
Perform schematic capture, simulations, and margin checks.
Measure timing, power, leakage, and optimize post-layout.
Collaborate with the layout team.
Validate SRAM designs (EM/IR, Power On, Lockup, etc.).
Support post-silicon efforts and debugging.
Preferred Proficiency in Python or Perl, Verilog, System Verilog.
Tools:
XA, AFS-Mega, HSPICE, NANOTIME, Virtuoso, Custom Compiler, XA-RA, Totem
Qualifications
Experience: 4-11 years
Degree: ME/M.tech in Electronic Engineering.
Responsibilities
Design FCI (Fast Cache instances) for x PU (CPU/GPU) systems with the SRAM team.
Define design specs with CPU/GPU/APU teams.
Optimize SRAM for power, timing, area, and yield.
Implement Single Port & Two Port SRAM circuits.
Perform schematic capture, simulations, and margin checks.
Measure timing, power, leakage, and optimize post-layout.
Collaborate with the layout team.
Validate SRAM designs (EM/IR, Power On, Lockup, etc.).
Support post-silicon efforts and debugging.
Preferred Proficiency in Python or Perl, Verilog, System Verilog.
Tools:
XA, AFS-Mega, HSPICE, NANOTIME, Virtuoso, Custom Compiler, XA-RA, Totem
Qualifications
Experience: 4-11 years
Degree: ME/M.tech in Electronic Engineering.