Job Description
Role Overview
As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers passionate about designing industry-leading CPU cores based on the revolutionary open‑source RISC‑V architecture.
Responsibilities
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration, generation of documentation, verification testbenches, tests, and packaged software.
- Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for perfo...