Job Description
Your Role
Key responsibilities in your new role
- Develop a deep understanding of complex IPs and contribute to the verification of these IPs
- Be responsible for developing System Verilog - UVM test bench components for IPs
- Be responsible for defining and writing a functional coverage model, write constrained random tests to randomly hit coverage targets
- Ensure the test bench meets sign-off targets, including coverage, functional safety, and test bench qualification
- Work on debug failing test cases to root cause
- Represent verification perspective and collaborate in Design and Concept meetings, contributing to enhancing the Verification strategy and architecture of IP test benches
- Proactively help increase the efficiency of verification activities and mitigate risks early
Your Profile
Qualifications And Skills To Help You Succeed
- A Bachelor's degree in Electrical/Electronic...